Tuesday, September 28, 2010

Paper watch: Custom transistor layout for RTS noise reduction in image sensors

I will make an effort to overlook the issues from the previous post and point to this nice paper at Electronics Letters describing a custom transistor layout for RTS noise reduction in image sensors: "Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors". The abstract reads:
Interface and near oxide traps in small gate area MOS transistors (gate area ≪1 μm2) lead to RTS noise which implies the emergence of noisy pixels in CMOS image sensors. To reduce this noise, two simple and efficient layout techniques of custom transistors have been imagined. These techniques have been successfully implemented in an image sensor test chip fabricated in a 0.35 μm CMOS image sensor process. Experimental results demonstrate a significant reduction of the noisy pixels for the two different techniques.
I like that the techniques have been "imagined" but also measured: Inception paper? :-)

One possible problem I see is that their transistors are done in a technology with LOCOS. Advanced technologies use STI, so I don't know how well the techniques translate to e.g. the latest CIS technologies by tsmc and others.

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