Monday, July 26, 2010

Paper watch

From the latest IEEXplore update, some interesting papers I found.

First, at the IEEE Electron Devices Letters, NXP engineers working on noise modeling report on excess noise for small channel devices:
Accurate modeling of thermal noise in MOSFETs is crucial for RF application of deep-submicrometer CMOS technologies. Here, we present RF noise measurements on four commercial advanced CMOS technologies down to the 45-nm node. Based on this extensive set of measurements, we prove the existence of excess noise (i.e., above the pure Nyquist level), but at the same time, we show that it is significant only for sub-100-nm MOSFETs. The amount of excess noise depends mainly on the channel length, and its occurrence is remarkably universal across technologies. We also present an electric-field-dependent extension of Nyquist's law that represents a nonequilibrium-transport correction to diffusive transport. We show that this microscopic model quantitatively explains the main features of the experimentally observed excess noise for all technologies. This includes its bias dependence, its geometrical scaling behavior, and the observed difference between n-channel and p-channel devices.

Next, three interesting papers at the Journal of Solid State Circuits, which changes editor-in-chief from Bram Nauta to Un-Ku Moon.

The first one is about "continuous-time" pipelined ADCs, where the continuous time refers to the first stage not being switched-capacitor. Interesting concept, although the FOM is not that impressive. And it still bothers me that one can quote 11 bit resolution with 56 dB SNDR. Additionally, they write in a figure that the ENOB is "9.09 dB".

More interesting is the one by Razavi on Cognitive Radio Design Challenges and Techniques:
Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes the issues related to the design of wideband signal paths and the decades-wide synthesis of carrier frequencies. A new CMOS low-noise amplifier topology for the range of 50 MHz to 10 GHz is introduced that achieves a noise figure of 2.9 to 5.7 dB with a power dissipation of 22 mW. Several multi-decade carrier generation techniques are proposed and a CMOS prototype is presented that exhibits a phase noise of -94 to -120 dBc/Hz at 1-MHz offset while consuming 31 mW.

And also the paper on "Progress and Challenges Towards Terahertz CMOS Integrated Circuits" is quite impressive:
Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community.

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