Monday, June 21, 2010

more 3D FPGAs

...and now also Toshiba:
[...] In the case of the 3D FPGA, SRAMs for configuration are formed by using amorphous Si TFT technology and stacked on a nine-layer CMOS chip that has copper (Cu) wiring and logic circuits for user logic. As a result, the chip area of the FPGA can be reduced to about half that of existing FPGAs.

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