Tuesday, June 29, 2010

Fun game

A fun nerdy game: arXiv vs. snarXiv (found here).

Monday, June 28, 2010

What is a patent?

From EETimes: "Supreme Court dodges decision of what is a patent".
"In general it was a pro-patenting ruling, and that collective sigh of relief you hear is from the software and biotech communities," said Reines. "A vote for the transformation test would have narrowed patents substantially for the software and biotech industries," he said.

Which way forward?

Harry "the ASIC guy" has a series of (so far) three interesting and thoughtful blog posts on the future direction for EDA:

High performance ADC PCB design

A very comprehensive article from TI on how to design the PCB for a high performance SAR ADC: "Optimizing SAR ADC performance by proper PCB layout".

Friday, June 25, 2010

Movable brain-machine interface

Here's a nice post at the Neurophilosophy blog about a movable brain-machine interface:
[...]
The device consists of an array of microelectrodes that are fabricated, along with a number of microscopic mechanical components, onto a silicon wafer. Each microelectrode is controlled by four microactuators, one each to deactivate a release-up lock and release-down lock, and one each to move the electrode up and down. The actuators work using electro-thermal strips and are coupled to a ratchet system that drives the centre shuttle of each electrode up or down.
[...]
The original article is here.

And related, at Mind Hacks, a link to an article on the US Army'svision for brain-machine interfaces.

Wednesday, June 23, 2010

Paper watch: Effects of Negative-Bias Operation and Optical Stress on Dark Current in CMOS Image Sensors

From the latest IEEE Transactions on Electron Devices, a paper from Hamamatsu on dark current mechanisms in pinned photodiodes: "Effects of Negative-Bias Operation and Optical Stress on Dark Current in CMOS Image Sensors". The abstract reads:
A negative-bias operation of the transfer gate has revealed a major origin of dark current defects of CMOS image sensors. Charge injection from the photodiode to the substrate at the negative-bias operation has been avoided by an improved well structure. A strong visible light has been observed to cause damage with an increase in the dark current under the normal operating condition, and the damage has been annealed in the power-off mode. This indicates that the strong light possibly causes a threshold voltage shift, which is explained by the photon-assisted tunneling or emission mechanisms. Multiple stress-and-anneal cycles have been found to cause an optical hardening effect, which can be explained by immobile trapped holes.

Graphene coming through

A couple of this week's graphene development announcements/papers:
  • A paper at Applied Physics Letters on graphene films for supercapacitors. Abstract: "This study reports the preparation of ultrathin, transparent graphene films for use in supercapacitor applications. The surface morphology of the films was investigated by scanning electron microscopy and transmission electron microscopy, revealing a very homogeneous surface with intimate contact between graphene sheets. Electrochemical characterization demonstrated nearly ideal electrical double layer capacitive behavior. The capacitance obtained from charge-discharge analysis is 135 F/g for a film of approximately 25 nm which has a transmittance of 70% at 550 nm and a high power density of 7200 W/kg in 2 M KCl electrolyte."
  • Advances on simplifying manufacturing nano-electronics based on graphene and nanowires: "[...]. They have devised a simple and quick one-step process based on thermochemical nanolithography (TCNL) for creating nanowires, tuning the electronic properties of reduced graphene oxide on the nanoscale and thereby allowing it to switch from being an insulating material to a conducting material."

DAC 2010 coverage collected

Sean Murphy is collecting blog posts, articles etc. regarding the DAC2010 conference here.

Tuesday, June 22, 2010

UMC gets into 3D stacking

The announcement at EETimes. Interesting that their plan is to apply it from the 28nm node onwards.

DAC wrap-up

DAC 2010 is finished. You can find a lot of information on the really good conference website. Don't miss the keynote's videos (but be careful, they tend to crash Firefox...).

A couple of wrap-ups:

Monday, June 21, 2010

more 3D FPGAs

...and now also Toshiba:
[...] In the case of the 3D FPGA, SRAMs for configuration are formed by using amorphous Si TFT technology and stacked on a nine-layer CMOS chip that has copper (Cu) wiring and logic circuits for user logic. As a result, the chip area of the FPGA can be reduced to about half that of existing FPGAs.

SPIE´s 2010 Security and Defense program online

The programs for the different parallel conferences of SPIE´s 2010 Security+Defense meeting are available here. Lots of IR and THz/mm wave imaging papers and posters, and a couple of presentations by Tower Jazz on their technology offers.

Sunday, June 20, 2010

Recent "more Moore" announcements

If we follow the naming convention of "more Moore" for those initiatives which push transistor scaling deeper into the nanometer regime, the last couple of weeks had some interesting new developments. In no particular order:
  • Toshiba shows its efforts for using nantotubes as transistor channels to achieve 16nm transistors.
  • Intel shows its use of "air gaps" (actually vacuum gaps) for metal insulation in 22nm technology.
  • Macronix announces its 3-D NAND flash (also at EETimes). For those with IEEEXplore access, one of the papers describing the technology during its development, from IEDM 2005, can be found here, showing that developments in this area take several years to reach the production stage. The abstract reads: "A bandgap engineered SONOS with greatly improved reliability properties is proposed. This concept is demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin "O1/N1/O2" serves as a non-trapping tunneling dielectric, N2 the high-trapping-rate charge storage layer, and O3 the blocking oxide. The ultra-thin "O1/N1/O2" provides a "modulated tunneling barrier" - it suppresses direct tunneling at low electric field during retention, while it allows efficient hole tunneling erase at high electric field due to the band offset. Therefore, this BE-SONOS offers fast hole tunneling erase, while it is immune to the retention problem of the conventional SONOS. With a N+-poly gate, we achieve self-convergent erased Vt ~3 V, suitable for NOR flash application. On the other hand, by using a P+-poly gate, a depletion mode device (Vt <> 6 V) is achieved, ideal for MLC-NAND application. Excellent performance and reliability for both applications are demonstrated. Furthermore, with this simple structure and no new materials BE-SONOS is readily manufacturable."

Wednesday, June 16, 2010

3D FPGAs

It seems that the big boys are putting their weight on this topic, and Xilinx and Actel are looking at 3D-stacked FPGAs, as this article points out.

Incidentally, this line almost at the end of the article made me wonder:
[...] Under the covers, there are two technical ways to make this all possible, according to an ARM insider. “The first is for TSVs at similar pitch to solder bumps (about 50nm)". [...]

Oh wait, do you mean it was a typo?

Thursday, June 10, 2010

Paper watch: Precise control of thermal conductivity at the nanoscale through individual phonon-scattering barriers

Seen at this German-language post at nanowerk, an interesting paper at Nature Materials: "Precise control of thermal conductivity at the nanoscale through individual phonon-scattering barriers". The abstract reads:
The ability to precisely control the thermal conductivity (κ) of a material is fundamental in the development of on-chip heat management or energy conversion applications. Nanostructuring permits a marked reduction of κ of single-crystalline materials, as recently demonstrated for silicon nanowires. However, silicon-based nanostructured materials with extremely low κ are not limited to nanowires. By engineering a set of individual phonon-scattering nanodot barriers we have accurately tailored the thermal conductivity of a single-crystalline SiGe material in spatially defined regions as short as ∼15 nm. Single-barrier thermal resistances between 2 and 4×10−9 m2 K W−1 were attained, resulting in a room-temperature κ down to about 0.9 W m−1 K−1, in multilayered structures with as little as five barriers. Such low thermal conductivity is compatible with a totally diffuse mismatch model for the barriers, and it is well below the amorphous limit. The results are in agreement with atomistic Green’s function simulations.

Wednesday, June 9, 2010

Videos at EETimes

EETimes hosts a large number of videos at their website ranging from demos, interviews and panels, such as the 2010 ESC SV Medical Electronics Panel.

Monday, June 7, 2010

PANalytical's PIXcel3D detector

It always makes you happy when something you have been a part of is successful. I read today that PANalytical has introduced in the market the first X-ray diffractometer with a hybrid X-ray pixel detector. I was there at the beginning of this work and it feels good to see it's finally out there.

Friday, June 4, 2010

Towards silicene

What if you could have all the advantages of graphene, but starting from Silicon (with the additional advantages that his means) instead of Carbon? Silicene might be the answer, and there are hints that it might be feasible, as this Applied Physics Letter shows: "Graphene-like silicon nanoribbons on Ag(110): A possible formation of silicene".
Scanning tunneling microscopy (STM) and ab initio calculations based on density functional theory (DFT) were used to study the self-aligned silicon nanoribbons on Ag(110) with honeycomb, graphene-like structure. The silicon honeycombs structure on top of the silver substrate is clearly observed by STM, while the DFT calculations confirm that the Si atoms adopt spontaneously this new silicon structure.

Although some people think it is not possible.

Paper watch: Nanostructured materials for photon detection

Inside the most recent Nature Nanotechnology journal (behind paywall), a nice overview of the progress in nanostructured materials for photo-detection. The abstract reads:
The detection of photons underpins imaging, spectroscopy, fibre-optic communications and time-gated distance measurements. Nanostructured materials are attractive for detection applications because they can be integrated with conventional silicon electronics and flexible, large-area substrates, and can be processed from the solution phase using established techniques such as spin casting, spray coating and layer-by-layer deposition. In addition, their performance has improved rapidly in recent years. Here we review progress in light sensing using nanostructured materials, focusing on solution-processed materials such as colloidal quantum dots and metal nanoparticles. These devices exhibit phenomena such as absorption of ultraviolet light, plasmonic enhancement of absorption, size-based spectral tuning, multiexciton generation, and charge carrier storage in surface and interface traps.

Thursday, June 3, 2010

More YouTube and image sensing

Looking at the related videos from the previous post, I find out about this cornucopia of videos from GoogleTechTalks' PhotoTechEdu series on photography and image sensing in general. Enjoy...

Altera FPGA and WDR image sensors

At Altera's YouTube channel there's this video on using FPGAs with WDR sensors. The demo uses an Aptina sensor.



Wednesday, June 2, 2010

Paper watch: Illumination-based synchronization of high speed image sensors

At the open access Sensors journal, an interesting application of the PLL concept from Tohoku University: "Illumination-Based Synchronization of High-Speed Vision Sensors".
To acquire images of dynamic scenes from multiple points of view simultaneously, the acquisition time of vision sensors should be synchronized. This paper describes an illumination-based synchronization method derived from the phase-locked loop (PLL) algorithm. Incident light to a vision sensor from an intensity-modulated illumination source serves as the reference signal for synchronization. Analog and digital computation within the vision sensor forms a PLL to regulate the output signal, which corresponds to the vision frame timing, to be synchronized with the reference. Simulated and experimental results show that a 1,000 Hz frame rate vision sensor was successfully synchronized with 32 μs jitters.

Tuesday, June 1, 2010

More on using visible light for data communication

Tech-on carries another news item about using visible light for data transmission:
The visible light communication system was developed by Outstanding Technology Co., Ltd. of Japan, a technology start-up. Performance in the lab has achieved transmission of a digital signal at 160Mbit/s over a 20cm distance with a single LED, and 13km transmission of a 1kbit/s-equivalent analog voice signal.
[...]
The firm combined a silver mirror with the photoreceptor to boost sensitivity and speed simultaneously. Concretely, light not directly received by the photoreceptor is reflected from the surrounding parabolic silver mirror into it.
The larger effective receptor area made it possible to use a high-speed (400MHz cut-off) photoreceptor and still achieve a high sensitivity of 1.5A/W to 2A/W output through 450nm wavelength. This is roughly ten times more sensitive than other photoreceptors with comparable waveband and speed.
[...]
While details of the new technology are still unknown, it was revealed that the modulation circuit design was based on accurate measurement of white LED resistive, capacitive and inductive components, making the success possible.