Wednesday, April 28, 2010

TSMC earnings call

Via Seeking Alpha.

Extracts:
[...] by technology, total wafer sales from 0.13 micron and below accounted for 71% of our total wafer sales representing 1 percentage point increase from last quarter. Meanwhile, the combined revenue from 40 nanometer and 65 nanometer already accounted for 41% of our total wafer sales. For 40 nanometer alone, revenue grew strongly in the first quarter as a result of strong customer demand and continued year improvement. 40 nanometer contributions jumped to 14% of our total wafer sales in the first quarter from 9% in fourth quarter '09. For 65 nanometer, revenue contribution was 27%. Meanwhile, 90 nanometer and 0.13 micron represented 17% and 13% of our total wafer sales, respectively.
[...]
As you can see, 40 nanometer is already in production. You probably have heard of TSMC's struggle with a year issue last year. Now, all these problems are behind us. We are doing very well. The defect in end stage is good or better than previous technology at this time – the same time after we released the technology.
[...]
For up to 20 nanometer we will continue to use planar transistor. Starting from 14 nanometer we will begin to – we will shift to the so-called FinFET transistor structure; the three dimension structure.
[...]
Moving forward, it is likely we will add more trend engineering and we will begin to use Germanium or Gallium Arsenide as channel material to enhance mobility.
[...]
So from physics point of view, especially from transistor, Moore's Law will be able to extend it to 7 nanometer based on everything we already know today.
[...]
CMOS image sensor. We are working with customers on 1.19 micron pixel, and TSMC is the first one to introduce this thing called BSI technology, backside illumination. There are certain advantages if we shine light from the backside, and in this case we had to slim down the wafer to 3 microns thick. The handling, the technology, extremely difficult. We already shipped products using this BSI technology in 8-inch wafers and we are working on 12-inch wafers right now.
Next. For the power device, we show example of this technology, give a breakdown voltage from 750 volts – that's not, I'm sorry, 700 volts to 850 volts. And in this area, there are many, many different applications for 12 volts, for 16 volts and just it requires a different way of optimizing these devices.
And next one is the MEMS technology. TSMC takes a special approach. We make CMOS on one wafer, MEMS another wafer and package on the third wafer and then we bond them together, and this particular case allowed us to optimize all three of them independently and then finally, we put them together.
Next please. On the package side I would just like to show you one example. We are – we began to work on 2D and 3D integration. This looking forward, I think before – especially after we – after the Moore's Law began to slow down, we still need a solution for system integration, and as 2D, 3D integration use silicon as a substrate, allowed us to make the entire system into a very small package with high performance and a low power. So we began to work on 3D stacking and a silicon interposer for 2D integration.
[...]
Related: EETimes on UMC's numbers.

1 comment:

  1. Congratulations for the blog David! I prefer this to image sensors world blog..
    Adi

    ReplyDelete

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