Wednesday, March 10, 2010

Innovation in FPGAs

Tierlogic announced today their new approach for FPGAs:
The TierLogic chip uses nine layers of metal which hold the core logic array, over which the configuration SRAM transistors are held in an amorphous silicon TFT layer on top of the metal layers. The TFT layer is currently made using 0.18 micron technology and is scalable.
"Since 2003 we've been, filing patents and working on process technology", says Hollingworth, "we've 50 patents granted and 20 pending. There are some wide patents, e.g. 'Any kind of 3D structure connected with programmable circuits'. The patents cover new forms of transistor. We had to design a process technology, not just a chip. No one has done majority carrier devices in TFTs before."
UPDATE: Ron Wilson expands.

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