Friday, December 18, 2009

Introduction to EMC

Via Test & Measurement World: Get Introduced to EMC.

Wednesday, December 16, 2009

3D Packaging

3DIncites starts a discussion on high aspect ratio TSVs, with a pdf of a presentation by Claudio Truzzi from Alchimer.

EETimes offers John Knickerbocker's five challenges for 3-D chip design.

Tuesday, December 15, 2009

Last IEDM 2009's posts

Withe IEDM over, these should be the last posts appearing about papers presented during the conference.
From Solid State Technology: "NEC tips low-resistance Cu interconnects, GaN power transistors on Si".
From Semiconductor International: "UMC Takes Hybrid Approach to 28 nm High-k".
From Small Times: "IEDM 2009: Stanford's CNT transistors".

Friday, December 11, 2009

Paper watch: image sensors papers at the Sensors journal

I recently pointed to a paper in the Sensors journal. I didn't notice at the time that one can see all papers related to a special issue on image sensors here. This issue is edited by Prof. Seitz from CSEM.

These two seem particularly interesting:

Today´s IEDM posts

From Semiconductor International: Intel Takes 32 nm PMOS to Record Levels.
From Tech-On: Japanese Researchers Develop SRAM Operating at 0.5V.

Tuesday, December 8, 2009

3D IC testing

A post at Semiconductor International: "3-D IC Test".

And an online discussion about to start at 3DInCites: "On the road to resolving test issues for 3D chip stacks".

Summary of IEDM course on scaling challenges

From Semiconductor International: "Silicon May Prevail Despite Power Fears".
Speakers at an IEDM short course on scaling challenges said planar devices made in bulk silicon CMOS are likely to continue to be the basic technology platform for the next decade, despite concerns about power consumption. While III-V and germanium channels offer high mobilities and lower operating voltages, the challenges of cost, manufacturing complexity, and finding a workable gate dielectric may prevent adoption. Scott Thompson, organizer of the short course, said one exception may be Intel, which he said is seriously considering a tri-gate transistor for the outer nodes.

Related: "HKMG: Gate-First vs Gate-Last Options".

Sunday, December 6, 2009


Stepping a little aside from the main focus of this blog, allow me to recommend this episode of the fantastic radio program Radiolab about numbers.

I didn't know that we humans are hardwired for logarithmic calculus (although some claim the evidence is not that conclusive).

And I hadn't heard of Benford's law either.

Jitter cheatsheet

Really nice poster from Agilent summarizing jitter issues linked in this blog post.

Friday, December 4, 2009

TSV reliability issues

Interesting article at Semiconductor International regarding TSV fabrication and reliability issues with regards to the metal used for the interconnect: "Researchers Strive for Copper TSV Reliability".
Thermomechanical reliability is a must in order for 3-D ICs to enter high-volume manufacturing, but concerns continue about the reliability of copper through-silicon vias (TSVs). The issue has researchers scrambling to cope with copper thermal mismatch issues in actual chips, as opposed to test structures.

Nanotech regulations

SPIE has an editorial article on regulation of nanotechnology risks: "Small concerns: nanotech regulations and risk management".
Nanomaterials have become a hot topic in the past decade, both for their advantages and hazards. Now The National Science Foundation says the nanotechnology industry could be worth $1 trillion by 2015, and would employ two million workers directly. Both governments and industry are looking at and addressing safety concerns, and determining the next steps for nanomaterial manufacturers and handlers.

Thursday, December 3, 2009

Wednesday, December 2, 2009

ISSCC 2010 preview

EETimes is carrying a series of articles previewing the coming ISSCC. Example: "Sensors make all the difference".

"Quantum" ghost imaging

Via NASA's Defense Tech Briefs I land on this news item from the US military. Googling I find this item at Bruce Schneier's blog with a very interesting discussion and detailed papers going on in the comments, including an older news item at New Scientist.

Seems interesting...

Paper watch: Integral imaging

From Applied Optics, an interesting open-for-everyone paper: "Recent progress in three-dimensional information processing based on integral imaging":
Recently developed integral imaging techniques are reviewed. Integral imaging captures and reproduces the light rays from the object space, enabling the acquisition and the display of the three-dimensional information of the object in an efficient way. Continuous effort on integral imaging has been improving the performance of the capture and display process in various aspects, including distortion, resolution, viewing angle, and depth range. Digital data processing of the captured light rays can now visualize the three-dimensional structure of the object with a high degree of freedom and enhanced quality. This recent progress is of high interest for both industrial applications and academic research.

Overview of 2009 technological breakthorughs in photonics

A really nice article at Laser Focus World worth its reading time: "TECHNOLOGY REVIEW 2009: Accelerated ingenuity".
The quantity and quality of innovation in photonics this past year was enormous, with many interesting achievements among the less publicized.

Overview of optical coatings technologies

From Laser Focus World: "HIGH-PERFORMANCE OPTICAL COATINGS: Tough requirements make for tough coatings".

Photonics West 2010 preview

Another conference preview. This time, SPIE's Photonic West 2010: "PHOTONICS WEST 2010: Moscone here we come!".

Organic SWIR photodetectors

From Laser Focus World, an article by Siemens Erlangen: "NEAR-INFRARED IMAGING: Hybrid photodiodes promise cost-effective short-wave IR imaging".

Transistor noise model

More info on the new transistor noise model for low-frequency noise (1/f and RTS) from SEMATECH: "New transistor noise model helps ID defects in gate stacks".
According to Michael Shur, professor at Rensselaer Polytechnic Institute, "The SEMATECH work explains several orders of magnitude difference between older, so-called, tunneling models and the noise measured in advanced CMOS with ultrathin oxide layers."

More on memristors

From ElectroIQ: "HP's Stan Williams: Hybrid CMOS-memristors, the future of analog".
A memristor is the fourth fundamental circuit element (resistor, capacitor, and inductor being the three other well-known circuit elements) that can be described using two equations: a quasi-static equation, and a dynamical equation. The memristor's properties, Williams explained, depend on time; the state variable depends on the device's past history. The consequences of these properties and characteristics are that the device's C-V characteristic curve is a pinched hysteresis loop; the voltage and current always have to be 0 at the same time, so the device cannot store charge or energy, but it can store information. "This is key and profound in terms of being able to build new types of electronic circuits," observed Williams.

Paul Rako's overview of ISSCC 2010

The always insightful and often entertaining Paul Rako gives an overview of the coming ISSCC based on the advance program.

One of the things that had me cracking up:
Paul’s Summary: This is entertaining for the same reason that PLLs are. A bunch of digital guys struggling with the fact that at a few GHz, nothing is digital. They so very much want ones and zeros and mother nature keeps giving them sine waves. And reflections. And noise. And all the other analog headaches you have known about your whole career. These poor schmucks have to learn VNAs (vector network analyzers) from the RF guys and TDR (time domain reflectometry) from the analog types. They also have to be up on field solvers. Sometimes they talk frequency domain and sometime they talk time domain. This is worth it just to see the glazed-over eyes in the audience as some presenter discusses doing a VNA calibration run. This section has the greatest number of exclamation points in the abstracts.