Wednesday, November 25, 2009

FPGA future

From EDN's Practical Chip Design blog: "A look into the future of FPGAs with Xilinx's Gavrielov and Rangasayee".

The argument between ASICs, ASSPs, and FPGAs has ranged over the same territory for a decade. FPGAs are slower, more power-hungry, and more expensive than comparable ASICs. But FPGAs require no NRE, require little physical design or verification, and provide prototypes in hours or days instead of weeks. In outline, the terms of the debate haven't changed: FPGAs make sense for low- to moderate-volume designs of low to moderate complexity, in which neither power nor performance is critical and there is no close fit in the ASSP world.

But this apparent stasis conceals a lot of activity at the margin, where the technologies have significant overlap. In part this activity is a gobbling of market share by FPGAs as a result of the global economic catastrophe. With end-user demand all but gone and returning only furtively, "moderate volume" includes a lot more designs than it used to, especially if management uses the 90-percent-confidence forecast instead of the "this is what it could do after a recovery" forecast. And that part about no NRE looms very large when there is no cash available for NRE.

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