Monday, November 30, 2009

Nanowire transistors

From Photonics.com: "Nanowire transistors realized".
[...] Whereas conventional transistors are made on flat, horizontal pieces of silicon, the silicon nanowires are "grown" vertically. Because of this vertical structure, they have a smaller footprint, which could make it possible to fit more transistors on an integrated circuit, or chip, Stach said.

"But first we need to learn how to manufacture nanowires to exacting standards before industry can start using them to produce transistors," he said.
[...]
(emphasis mine).

Friday, November 27, 2009

New issue of 3D packaging news

By Yole Development, the December issue can be downloaded here.

Thursday, November 26, 2009

Anti-matter in Earth’s stratosphere churns out gamma rays

It's not electronics per se, but it's still pretty interesting. From the Knight Science Journalism Tracker.

Room temperature spintronics

From EETimes: "Researchers report room-temperature silicon spintronics".

For those with access to Nature, the article is here.

Paper watch: Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique

From Sensors journal (open access): "Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique":
The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied. The results show that the non-linearity is caused by two factors, namely the current diffusion, which has an exponential relation with the potential barrier, and the initial condition of photodiodes in which it shows that the error in the high illumination region increases as the ratio of the long to the short accumulation time raises. Moreover, the increment of the saturation level of photodiodes also increases the error in the high illumination region.

New batch of tutorials

From Low-Power Design: "Active Noise Cancellation Comes to Mobile Phones" by Wolfson Microelectronics.

From EDN:

Wednesday, November 25, 2009

Ten emerging technologies to watch in 2010

At EDA Design Line.

On shielding

From Design News:"An Update on Shielding".
The comments below the article are also interesting.

FPGA future

From EDN's Practical Chip Design blog: "A look into the future of FPGAs with Xilinx's Gavrielov and Rangasayee".

The argument between ASICs, ASSPs, and FPGAs has ranged over the same territory for a decade. FPGAs are slower, more power-hungry, and more expensive than comparable ASICs. But FPGAs require no NRE, require little physical design or verification, and provide prototypes in hours or days instead of weeks. In outline, the terms of the debate haven't changed: FPGAs make sense for low- to moderate-volume designs of low to moderate complexity, in which neither power nor performance is critical and there is no close fit in the ASSP world.

But this apparent stasis conceals a lot of activity at the margin, where the technologies have significant overlap. In part this activity is a gobbling of market share by FPGAs as a result of the global economic catastrophe. With end-user demand all but gone and returning only furtively, "moderate volume" includes a lot more designs than it used to, especially if management uses the 90-percent-confidence forecast instead of the "this is what it could do after a recovery" forecast. And that part about no NRE looms very large when there is no cash available for NRE.

Signal Integrity: shaping edges

From EDN:
There are many ways to make properly shaped signal edges, but they are each equivalent to some linear filtering operation.

Reducing EMI in Class D Audio Applications by Spread Spectrum Modulation Techniques

From Low Power Design, by B. McCulley from National Semi.

Virtual brain surgery using optical coherence tomography

From Photonics.com.
[...]
More precisely, Kang is building a tool to help brain surgeons locate and get a clear look at cancerous tissue. In some cases, Kang says, this device could eliminate the need to cut into the brain for a traditional biopsy, a procedure that can pose risks to the patient.

“The idea,” he says, “is to provide instant high-resolution pictures of a small segment of the brain without actually touching the tissue. These pictures could let the doctor conduct a ‘virtual biopsy’ to see where the tumor is and whether it is benign or malignant. And when it’s time to cut out the cancer, these images could help a surgeon see and avoid healthy tissue.”
[...]
Optical Coherence Tomography @ Wikipedia.

Tuesday, November 24, 2009

News regarding ROHS

Via EDN's Critical links blog: "ROHS to cover all electrical and electronic equipment?".

Strangely enough, I have the impression that this seems to be a bigger deal in the US than in Europe.

More on FinFETs

Also via IEEE Spectrum: "First Gallium-Based FinFETs":

[...]

At next month’s IEEE International Electron Devices Meeting, Ye’s group will report the creation of InGaAs FinFETs. The research shows that these FinFETs—with fins ranging from 100 nanometers to 200 nm in length—leaked less current and reduced other short-channel effects compared with ordinary InGaAs devices.

That’s useful, because short-channel effects such as current leakage are even more pronounced for III-V semiconductors like gallium arsenide (so called because they’re made from elements in the third and fifth columns of the right side of the periodic table).

Scientific debate...of sorts

Via IEEE Spectrum: "Cat Fight Brews Over Cat Brain":
[...] That the Bell prize would be awarded for such nonsense is beyond belief. I never realized that such trivial and unethical behavior would actually be rewarded. I would have expected an ethics committee to string this guy up by the toes. [...]

ISSCC 2010 program online

It's here (PDF).

IEEEXplore watch: A pixel-shared CMOS image sensor using lateral overflow gate

From the proceedings of ESSCIRC 2009:
A lateral overflow integration capacitor (LOFIC) based CMOS image sensor sharing two pixels and without row-select transistors has been developed using a newly added lateral overflow gate which directly connects the photodiode and the LOFIC. A 0.18-µm, 2-Poly 3-Metal CMOS technology with a buried pinned photodiode process was employed for the fabrication of the CMOS image sensor having 1/3.3-inch optical format, 1280H × 960V pixels, and RGB Bayer color filter and on-chip micro-lens on each pixel. The fabricated CMOS image sensor exhibits a high conversion gain of 84-µV/e- and a high full well capacity of 6.9 × 104-e- in spite of its pixel size of 3.0 × 3.0-µm2.

Monday, November 23, 2009

IEEEXplore watch: overview of direct conversion X-ray detectors

From the August issue of the IEEE Transactions on Nuclear Science: "Status of Direct Conversion Detectors for Medical Imaging With X-Rays":
Imaging detectors for medical X-ray and computed tomography (CT) applications have undergone many improvements and technology changes over time. But most (dynamic) detectors sold in this field still rely on indirect conversion, using scintillators and photodiodes to convert the X-ray quanta ultimately into electrical signals. Direct conversion detectors promise very high spatial resolution and high signal-to-noise ratios. Some direct conversion materials may allow for counting or even energy resolving detection of the X-ray quanta. Based on this, for example spectrally resolving CT systems are becoming an interesting option for the next decade. This contribution highlights the requirements of advanced medical X-ray and CT imaging and reviews examples of status and progress in the field. The emphasis is on the direct conversion sensors for pixelated detectors, but considerations on read-out concepts and on associated challenges such as interconnects will also be presented. Finally, the most burning issues, such as count rate limitations and polarization effects, will be discussed from an application point of view.

Comparing SOI and bulf FinFETs

Article at ElectroIQ taken from Solid State Technology:
This article compares the performance, process variability, and cost of speculative FinFET process flows based on SOI and bulk silicon substrates. While both SOI and bulk FinFETs should be able to achieve comparable performance, a bulk FinFET fabrication flow will require more process complexity. In SOI wafers, the buried oxide layer isolates individual transistors, while in bulk devices, isolation must be created by the wafer process. We show that, because the bulk FinFET process is more complex, it will lead to 140-160% more device variability, and thus to significant manufacturing and process control challenges. Though SOI substrates are more expensive, the costs of the more complex bulk FinFET process largely offset this expense, resulting in a roughly equivalent cost basis with bulk at production volumes.

Reboot

I'm restarting the blog. The idea changes a bit in that I will probably use it as more of a content aggregator of stuff I find which is interesting. This means posts will be shorter and happen more often.