Monday, June 29, 2009

A taxonomy of 3D interconnect technologies

From this month's IEEE International Interconnect Technologies Conference, the paper "3D technologies: Requiring more than 3 dimensions from concept to product" by IMEC's Bart Swinnen offers a classification of 3D interconnects. An extract:

Classifying 3D interconnects according to their level in the system wiring hierarchy, we distinguish the following levels:

  • 3D Package-On-Package (3D-POP): [...] The 3D interconnect is fabricated at die level and using mature assembly techniques. This results in a highly manufacturable and flexible technology that can adapt quickly to changes in layout and routing in the dies to stack. The short time-to-market is a primary business drive that renders this technology particularly attractive [...]. JEDEC standards for the 3D-POP platform are available and the method is in production today. [...]
  • 3D System In Package (3D-SIP): [...] The 3D interconnect is fabricated at die level using mature packaging techniques such as wire bonding. Again the result is a highly manufacturable and flexible technology. [...]
  • 3D Wafer Level Packaging (3D-WLP): [...] Here the 3D interconnect is a through-substrate via. Contrary to the 3D-POP and 3D-SIP cases, the 3D interconnect here is fabricated at wafer level. [...] The 3D-WLP solution aims at providing a chip scale solution for interconnection at bond pad level. Therefore the technology is attractive for compact, heterogeneously integrated systems. [...] Market introduction of 3D-WLP solutions occurred in early 2008 when the first TSV-based CMOS Image Sensors appeared on the market.
  • 3D Stacked Integrated Circuit (3D-SIC): 3D-SIC is the first 3D solution described here that aims to shortcut an on-chip interconnect level. [...] Therefore the technology is well positioned for high bandwidth logic to memory interconnection such as required for handheld video applications. As in this case the TSV appears below the bond pad level, the 3D interconnects here have a much lower capacitance than the classical non-3D interconnects. This additionally enables power savings that make the technology attractive for mobile products. This technology is not yet in production today.
  • 3D Integrated Circuit (3D IC): This solution provide 3D interconnects that features at the local interconnect level of the BEOL wiring hierarchy. [...] The reduced signal latency and power consumption are appealing features to implement the technology in high performance 3D-logic and 3D-memory products.

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