Monday, June 29, 2009

A taxonomy of 3D interconnect technologies

From this month's IEEE International Interconnect Technologies Conference, the paper "3D technologies: Requiring more than 3 dimensions from concept to product" by IMEC's Bart Swinnen offers a classification of 3D interconnects. An extract:

Classifying 3D interconnects according to their level in the system wiring hierarchy, we distinguish the following levels:

  • 3D Package-On-Package (3D-POP): [...] The 3D interconnect is fabricated at die level and using mature assembly techniques. This results in a highly manufacturable and flexible technology that can adapt quickly to changes in layout and routing in the dies to stack. The short time-to-market is a primary business drive that renders this technology particularly attractive [...]. JEDEC standards for the 3D-POP platform are available and the method is in production today. [...]
  • 3D System In Package (3D-SIP): [...] The 3D interconnect is fabricated at die level using mature packaging techniques such as wire bonding. Again the result is a highly manufacturable and flexible technology. [...]
  • 3D Wafer Level Packaging (3D-WLP): [...] Here the 3D interconnect is a through-substrate via. Contrary to the 3D-POP and 3D-SIP cases, the 3D interconnect here is fabricated at wafer level. [...] The 3D-WLP solution aims at providing a chip scale solution for interconnection at bond pad level. Therefore the technology is attractive for compact, heterogeneously integrated systems. [...] Market introduction of 3D-WLP solutions occurred in early 2008 when the first TSV-based CMOS Image Sensors appeared on the market.
  • 3D Stacked Integrated Circuit (3D-SIC): 3D-SIC is the first 3D solution described here that aims to shortcut an on-chip interconnect level. [...] Therefore the technology is well positioned for high bandwidth logic to memory interconnection such as required for handheld video applications. As in this case the TSV appears below the bond pad level, the 3D interconnects here have a much lower capacitance than the classical non-3D interconnects. This additionally enables power savings that make the technology attractive for mobile products. This technology is not yet in production today.
  • 3D Integrated Circuit (3D IC): This solution provide 3D interconnects that features at the local interconnect level of the BEOL wiring hierarchy. [...] The reduced signal latency and power consumption are appealing features to implement the technology in high performance 3D-logic and 3D-memory products.

Sunday, June 21, 2009


From Cypress Semiconductors, an introduction to capacitive proximity sensing.


Fundamental university research (hence do not expect a camera in one year), but still interesting research in quantum avalanche photodetection (paper).


A video showing how a microphone is made.


Networking sensors in hospitals.

Moore's law and beyond

A lot of things going on in research on new devices and CMOS scaling. Continuing from last week's post.

Signal integrity

A funny list at the Signal Integrity list: Top 10 reasons not to care about signal integrity.

And from the same source, some papers from a recent ADS User Group Meeting.

System Design

An interesting overview of USB 3.0 challenges at the PHY level.

Steve Leibson points to a white paper on graphics accelerators.


I really liked this post by Eric Bogatin: Are electronics specs really established by a horse’s ass? 

A summary of specifications for ADCs in communication applications.

3D-IC technology

This study shows that flip-chip is becoming a competitive solution.

The next step is of course 3D-IC technology, as long as the current hurdles are removed, something for which industry and research institutions go together. A few links to recent developments:

Reverse engineering

From the fine folks at Chipworks:

Sunday, June 14, 2009

Packaging Technologies

On new PCB technologies for medical devices:

ERMF is still a relatively new process that holds far more potential than is currently being tapped. The precise and repeatable nature of the technology holds great potential because of the enabling effect it affords the designer of implantable medical devices and other applications that have similar size and material limitations.


On multipurpose integrated contact lenses:

The next challenge will be to integrate all the above functions and yield the first fully functional and stand-alone wireless contact lens. The day that such a device can be demonstrated may be much nearer than was imagined even a short while ago.


Several interesting articles on 3C-ICs from Semiconductor International:

Semiconductor Technologies

"Graphene May Have Advantages Over Copper For Future IC Interconnects":

Beyond resistivity improvement, graphene interconnects would offer higher electron mobility, better thermal conductivity, higher mechanical strength and reduced capacitance coupling between adjacent wires.


Because graphene can be patterned using conventional microelectronics processes, the transition from copper could be made without integrating a new manufacturing technique into circuit fabrication.


Scientists at the Forschungszentrum Dresden-Rossendorf (FZD) research center have been able to produce superconducting germanium for the first time.


At Semiconductor International: "IMEC Tips 10 nm Options at Tech Forum". One line that links nicely with the last paragraphs of the previous article:

Heyns said that recent studies at IMEC revealed that germanium oxide (GeO2), when grown under the right conditions on silicon, is actually a better insulator than the SiO2.

And the last paragraph, linking to the first article above:

Graphene, which is a zero-bandgap semiconductor with very high carrier mobility, is showing great promise, particularly for interconnects. While the current capacity for copper is ~106 A/cm2, it is ~109 A/cm2 for carbon nanotubes.

Thursday, June 11, 2009

Updates coming

Been on holiday the last weeks. Updates coming this weekend.