Friday, December 18, 2009

Introduction to EMC

Via Test & Measurement World: Get Introduced to EMC.

Wednesday, December 16, 2009

3D Packaging

3DIncites starts a discussion on high aspect ratio TSVs, with a pdf of a presentation by Claudio Truzzi from Alchimer.

EETimes offers John Knickerbocker's five challenges for 3-D chip design.

Tuesday, December 15, 2009

Last IEDM 2009's posts

Withe IEDM over, these should be the last posts appearing about papers presented during the conference.
From Solid State Technology: "NEC tips low-resistance Cu interconnects, GaN power transistors on Si".
From Semiconductor International: "UMC Takes Hybrid Approach to 28 nm High-k".
From Small Times: "IEDM 2009: Stanford's CNT transistors".

Friday, December 11, 2009

Paper watch: image sensors papers at the Sensors journal

I recently pointed to a paper in the Sensors journal. I didn't notice at the time that one can see all papers related to a special issue on image sensors here. This issue is edited by Prof. Seitz from CSEM.

These two seem particularly interesting:

Today´s IEDM posts

From Semiconductor International: Intel Takes 32 nm PMOS to Record Levels.
From Tech-On: Japanese Researchers Develop SRAM Operating at 0.5V.

Tuesday, December 8, 2009

3D IC testing

A post at Semiconductor International: "3-D IC Test".

And an online discussion about to start at 3DInCites: "On the road to resolving test issues for 3D chip stacks".

Summary of IEDM course on scaling challenges

From Semiconductor International: "Silicon May Prevail Despite Power Fears".
Speakers at an IEDM short course on scaling challenges said planar devices made in bulk silicon CMOS are likely to continue to be the basic technology platform for the next decade, despite concerns about power consumption. While III-V and germanium channels offer high mobilities and lower operating voltages, the challenges of cost, manufacturing complexity, and finding a workable gate dielectric may prevent adoption. Scott Thompson, organizer of the short course, said one exception may be Intel, which he said is seriously considering a tri-gate transistor for the outer nodes.

Related: "HKMG: Gate-First vs Gate-Last Options".

Sunday, December 6, 2009


Stepping a little aside from the main focus of this blog, allow me to recommend this episode of the fantastic radio program Radiolab about numbers.

I didn't know that we humans are hardwired for logarithmic calculus (although some claim the evidence is not that conclusive).

And I hadn't heard of Benford's law either.

Jitter cheatsheet

Really nice poster from Agilent summarizing jitter issues linked in this blog post.

Friday, December 4, 2009

TSV reliability issues

Interesting article at Semiconductor International regarding TSV fabrication and reliability issues with regards to the metal used for the interconnect: "Researchers Strive for Copper TSV Reliability".
Thermomechanical reliability is a must in order for 3-D ICs to enter high-volume manufacturing, but concerns continue about the reliability of copper through-silicon vias (TSVs). The issue has researchers scrambling to cope with copper thermal mismatch issues in actual chips, as opposed to test structures.

Nanotech regulations

SPIE has an editorial article on regulation of nanotechnology risks: "Small concerns: nanotech regulations and risk management".
Nanomaterials have become a hot topic in the past decade, both for their advantages and hazards. Now The National Science Foundation says the nanotechnology industry could be worth $1 trillion by 2015, and would employ two million workers directly. Both governments and industry are looking at and addressing safety concerns, and determining the next steps for nanomaterial manufacturers and handlers.

Thursday, December 3, 2009

Wednesday, December 2, 2009

ISSCC 2010 preview

EETimes is carrying a series of articles previewing the coming ISSCC. Example: "Sensors make all the difference".

"Quantum" ghost imaging

Via NASA's Defense Tech Briefs I land on this news item from the US military. Googling I find this item at Bruce Schneier's blog with a very interesting discussion and detailed papers going on in the comments, including an older news item at New Scientist.

Seems interesting...

Paper watch: Integral imaging

From Applied Optics, an interesting open-for-everyone paper: "Recent progress in three-dimensional information processing based on integral imaging":
Recently developed integral imaging techniques are reviewed. Integral imaging captures and reproduces the light rays from the object space, enabling the acquisition and the display of the three-dimensional information of the object in an efficient way. Continuous effort on integral imaging has been improving the performance of the capture and display process in various aspects, including distortion, resolution, viewing angle, and depth range. Digital data processing of the captured light rays can now visualize the three-dimensional structure of the object with a high degree of freedom and enhanced quality. This recent progress is of high interest for both industrial applications and academic research.

Overview of 2009 technological breakthorughs in photonics

A really nice article at Laser Focus World worth its reading time: "TECHNOLOGY REVIEW 2009: Accelerated ingenuity".
The quantity and quality of innovation in photonics this past year was enormous, with many interesting achievements among the less publicized.

Overview of optical coatings technologies

From Laser Focus World: "HIGH-PERFORMANCE OPTICAL COATINGS: Tough requirements make for tough coatings".

Photonics West 2010 preview

Another conference preview. This time, SPIE's Photonic West 2010: "PHOTONICS WEST 2010: Moscone here we come!".

Organic SWIR photodetectors

From Laser Focus World, an article by Siemens Erlangen: "NEAR-INFRARED IMAGING: Hybrid photodiodes promise cost-effective short-wave IR imaging".

Transistor noise model

More info on the new transistor noise model for low-frequency noise (1/f and RTS) from SEMATECH: "New transistor noise model helps ID defects in gate stacks".
According to Michael Shur, professor at Rensselaer Polytechnic Institute, "The SEMATECH work explains several orders of magnitude difference between older, so-called, tunneling models and the noise measured in advanced CMOS with ultrathin oxide layers."

More on memristors

From ElectroIQ: "HP's Stan Williams: Hybrid CMOS-memristors, the future of analog".
A memristor is the fourth fundamental circuit element (resistor, capacitor, and inductor being the three other well-known circuit elements) that can be described using two equations: a quasi-static equation, and a dynamical equation. The memristor's properties, Williams explained, depend on time; the state variable depends on the device's past history. The consequences of these properties and characteristics are that the device's C-V characteristic curve is a pinched hysteresis loop; the voltage and current always have to be 0 at the same time, so the device cannot store charge or energy, but it can store information. "This is key and profound in terms of being able to build new types of electronic circuits," observed Williams.

Paul Rako's overview of ISSCC 2010

The always insightful and often entertaining Paul Rako gives an overview of the coming ISSCC based on the advance program.

One of the things that had me cracking up:
Paul’s Summary: This is entertaining for the same reason that PLLs are. A bunch of digital guys struggling with the fact that at a few GHz, nothing is digital. They so very much want ones and zeros and mother nature keeps giving them sine waves. And reflections. And noise. And all the other analog headaches you have known about your whole career. These poor schmucks have to learn VNAs (vector network analyzers) from the RF guys and TDR (time domain reflectometry) from the analog types. They also have to be up on field solvers. Sometimes they talk frequency domain and sometime they talk time domain. This is worth it just to see the glazed-over eyes in the audience as some presenter discusses doing a VNA calibration run. This section has the greatest number of exclamation points in the abstracts.

Monday, November 30, 2009

Nanowire transistors

From "Nanowire transistors realized".
[...] Whereas conventional transistors are made on flat, horizontal pieces of silicon, the silicon nanowires are "grown" vertically. Because of this vertical structure, they have a smaller footprint, which could make it possible to fit more transistors on an integrated circuit, or chip, Stach said.

"But first we need to learn how to manufacture nanowires to exacting standards before industry can start using them to produce transistors," he said.
(emphasis mine).

Friday, November 27, 2009

New issue of 3D packaging news

By Yole Development, the December issue can be downloaded here.

Thursday, November 26, 2009

Anti-matter in Earth’s stratosphere churns out gamma rays

It's not electronics per se, but it's still pretty interesting. From the Knight Science Journalism Tracker.

Room temperature spintronics

From EETimes: "Researchers report room-temperature silicon spintronics".

For those with access to Nature, the article is here.

Paper watch: Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique

From Sensors journal (open access): "Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique":
The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied. The results show that the non-linearity is caused by two factors, namely the current diffusion, which has an exponential relation with the potential barrier, and the initial condition of photodiodes in which it shows that the error in the high illumination region increases as the ratio of the long to the short accumulation time raises. Moreover, the increment of the saturation level of photodiodes also increases the error in the high illumination region.

New batch of tutorials

From Low-Power Design: "Active Noise Cancellation Comes to Mobile Phones" by Wolfson Microelectronics.

From EDN:

Wednesday, November 25, 2009

Ten emerging technologies to watch in 2010

At EDA Design Line.

On shielding

From Design News:"An Update on Shielding".
The comments below the article are also interesting.

FPGA future

From EDN's Practical Chip Design blog: "A look into the future of FPGAs with Xilinx's Gavrielov and Rangasayee".

The argument between ASICs, ASSPs, and FPGAs has ranged over the same territory for a decade. FPGAs are slower, more power-hungry, and more expensive than comparable ASICs. But FPGAs require no NRE, require little physical design or verification, and provide prototypes in hours or days instead of weeks. In outline, the terms of the debate haven't changed: FPGAs make sense for low- to moderate-volume designs of low to moderate complexity, in which neither power nor performance is critical and there is no close fit in the ASSP world.

But this apparent stasis conceals a lot of activity at the margin, where the technologies have significant overlap. In part this activity is a gobbling of market share by FPGAs as a result of the global economic catastrophe. With end-user demand all but gone and returning only furtively, "moderate volume" includes a lot more designs than it used to, especially if management uses the 90-percent-confidence forecast instead of the "this is what it could do after a recovery" forecast. And that part about no NRE looms very large when there is no cash available for NRE.

Signal Integrity: shaping edges

From EDN:
There are many ways to make properly shaped signal edges, but they are each equivalent to some linear filtering operation.

Reducing EMI in Class D Audio Applications by Spread Spectrum Modulation Techniques

From Low Power Design, by B. McCulley from National Semi.

Virtual brain surgery using optical coherence tomography

More precisely, Kang is building a tool to help brain surgeons locate and get a clear look at cancerous tissue. In some cases, Kang says, this device could eliminate the need to cut into the brain for a traditional biopsy, a procedure that can pose risks to the patient.

“The idea,” he says, “is to provide instant high-resolution pictures of a small segment of the brain without actually touching the tissue. These pictures could let the doctor conduct a ‘virtual biopsy’ to see where the tumor is and whether it is benign or malignant. And when it’s time to cut out the cancer, these images could help a surgeon see and avoid healthy tissue.”
Optical Coherence Tomography @ Wikipedia.

Tuesday, November 24, 2009

News regarding ROHS

Via EDN's Critical links blog: "ROHS to cover all electrical and electronic equipment?".

Strangely enough, I have the impression that this seems to be a bigger deal in the US than in Europe.

More on FinFETs

Also via IEEE Spectrum: "First Gallium-Based FinFETs":


At next month’s IEEE International Electron Devices Meeting, Ye’s group will report the creation of InGaAs FinFETs. The research shows that these FinFETs—with fins ranging from 100 nanometers to 200 nm in length—leaked less current and reduced other short-channel effects compared with ordinary InGaAs devices.

That’s useful, because short-channel effects such as current leakage are even more pronounced for III-V semiconductors like gallium arsenide (so called because they’re made from elements in the third and fifth columns of the right side of the periodic table).

Scientific debate...of sorts

Via IEEE Spectrum: "Cat Fight Brews Over Cat Brain":
[...] That the Bell prize would be awarded for such nonsense is beyond belief. I never realized that such trivial and unethical behavior would actually be rewarded. I would have expected an ethics committee to string this guy up by the toes. [...]

ISSCC 2010 program online

It's here (PDF).

IEEEXplore watch: A pixel-shared CMOS image sensor using lateral overflow gate

From the proceedings of ESSCIRC 2009:
A lateral overflow integration capacitor (LOFIC) based CMOS image sensor sharing two pixels and without row-select transistors has been developed using a newly added lateral overflow gate which directly connects the photodiode and the LOFIC. A 0.18-µm, 2-Poly 3-Metal CMOS technology with a buried pinned photodiode process was employed for the fabrication of the CMOS image sensor having 1/3.3-inch optical format, 1280H × 960V pixels, and RGB Bayer color filter and on-chip micro-lens on each pixel. The fabricated CMOS image sensor exhibits a high conversion gain of 84-µV/e- and a high full well capacity of 6.9 × 104-e- in spite of its pixel size of 3.0 × 3.0-µm2.

Monday, November 23, 2009

IEEEXplore watch: overview of direct conversion X-ray detectors

From the August issue of the IEEE Transactions on Nuclear Science: "Status of Direct Conversion Detectors for Medical Imaging With X-Rays":
Imaging detectors for medical X-ray and computed tomography (CT) applications have undergone many improvements and technology changes over time. But most (dynamic) detectors sold in this field still rely on indirect conversion, using scintillators and photodiodes to convert the X-ray quanta ultimately into electrical signals. Direct conversion detectors promise very high spatial resolution and high signal-to-noise ratios. Some direct conversion materials may allow for counting or even energy resolving detection of the X-ray quanta. Based on this, for example spectrally resolving CT systems are becoming an interesting option for the next decade. This contribution highlights the requirements of advanced medical X-ray and CT imaging and reviews examples of status and progress in the field. The emphasis is on the direct conversion sensors for pixelated detectors, but considerations on read-out concepts and on associated challenges such as interconnects will also be presented. Finally, the most burning issues, such as count rate limitations and polarization effects, will be discussed from an application point of view.

Comparing SOI and bulf FinFETs

Article at ElectroIQ taken from Solid State Technology:
This article compares the performance, process variability, and cost of speculative FinFET process flows based on SOI and bulk silicon substrates. While both SOI and bulk FinFETs should be able to achieve comparable performance, a bulk FinFET fabrication flow will require more process complexity. In SOI wafers, the buried oxide layer isolates individual transistors, while in bulk devices, isolation must be created by the wafer process. We show that, because the bulk FinFET process is more complex, it will lead to 140-160% more device variability, and thus to significant manufacturing and process control challenges. Though SOI substrates are more expensive, the costs of the more complex bulk FinFET process largely offset this expense, resulting in a roughly equivalent cost basis with bulk at production volumes.


I'm restarting the blog. The idea changes a bit in that I will probably use it as more of a content aggregator of stuff I find which is interesting. This means posts will be shorter and happen more often.

Saturday, September 5, 2009

On hiatus...

As must be clear by now, this blog is currently on hiatus, and will very likely remain like this for one or two more months.

Wednesday, July 8, 2009

3D-IC online experts' discussion

A promising online discussion during the month of July on issues related to 3D-IC technology here.

Sunday, July 5, 2009

Brain interfaces

Seen at the very good Mind Hacks blog: a freely available special issue of the Neurosurgical/Focus journal on Advances in brain-machine interfaces, and a list of papers on deep brain stimulation hardware issues.

And also there is this introduction to the Brian simulator for spiking neural modeling.

TeraHertz research

This area of research is steadily gaining momentum, together with mm-wave. The NTT Laboratories introduce the areas in this white paper. And from the Fraunhofer Institute, this article talks about a THz imaging system.

Energy and Power

Again, a collection of links about energy and power issues. From the big to the small.


In the big:


In the "medium":


In the small:

Systems design

A collection of articles on designing complex systems:

Monday, June 29, 2009

A taxonomy of 3D interconnect technologies

From this month's IEEE International Interconnect Technologies Conference, the paper "3D technologies: Requiring more than 3 dimensions from concept to product" by IMEC's Bart Swinnen offers a classification of 3D interconnects. An extract:

Classifying 3D interconnects according to their level in the system wiring hierarchy, we distinguish the following levels:

  • 3D Package-On-Package (3D-POP): [...] The 3D interconnect is fabricated at die level and using mature assembly techniques. This results in a highly manufacturable and flexible technology that can adapt quickly to changes in layout and routing in the dies to stack. The short time-to-market is a primary business drive that renders this technology particularly attractive [...]. JEDEC standards for the 3D-POP platform are available and the method is in production today. [...]
  • 3D System In Package (3D-SIP): [...] The 3D interconnect is fabricated at die level using mature packaging techniques such as wire bonding. Again the result is a highly manufacturable and flexible technology. [...]
  • 3D Wafer Level Packaging (3D-WLP): [...] Here the 3D interconnect is a through-substrate via. Contrary to the 3D-POP and 3D-SIP cases, the 3D interconnect here is fabricated at wafer level. [...] The 3D-WLP solution aims at providing a chip scale solution for interconnection at bond pad level. Therefore the technology is attractive for compact, heterogeneously integrated systems. [...] Market introduction of 3D-WLP solutions occurred in early 2008 when the first TSV-based CMOS Image Sensors appeared on the market.
  • 3D Stacked Integrated Circuit (3D-SIC): 3D-SIC is the first 3D solution described here that aims to shortcut an on-chip interconnect level. [...] Therefore the technology is well positioned for high bandwidth logic to memory interconnection such as required for handheld video applications. As in this case the TSV appears below the bond pad level, the 3D interconnects here have a much lower capacitance than the classical non-3D interconnects. This additionally enables power savings that make the technology attractive for mobile products. This technology is not yet in production today.
  • 3D Integrated Circuit (3D IC): This solution provide 3D interconnects that features at the local interconnect level of the BEOL wiring hierarchy. [...] The reduced signal latency and power consumption are appealing features to implement the technology in high performance 3D-logic and 3D-memory products.

Sunday, June 21, 2009


From Cypress Semiconductors, an introduction to capacitive proximity sensing.


Fundamental university research (hence do not expect a camera in one year), but still interesting research in quantum avalanche photodetection (paper).


A video showing how a microphone is made.


Networking sensors in hospitals.

Moore's law and beyond

A lot of things going on in research on new devices and CMOS scaling. Continuing from last week's post.

Signal integrity

A funny list at the Signal Integrity list: Top 10 reasons not to care about signal integrity.

And from the same source, some papers from a recent ADS User Group Meeting.

System Design

An interesting overview of USB 3.0 challenges at the PHY level.

Steve Leibson points to a white paper on graphics accelerators.


I really liked this post by Eric Bogatin: Are electronics specs really established by a horse’s ass? 

A summary of specifications for ADCs in communication applications.

3D-IC technology

This study shows that flip-chip is becoming a competitive solution.

The next step is of course 3D-IC technology, as long as the current hurdles are removed, something for which industry and research institutions go together. A few links to recent developments:

Reverse engineering

From the fine folks at Chipworks:

Sunday, June 14, 2009

Packaging Technologies

On new PCB technologies for medical devices:

ERMF is still a relatively new process that holds far more potential than is currently being tapped. The precise and repeatable nature of the technology holds great potential because of the enabling effect it affords the designer of implantable medical devices and other applications that have similar size and material limitations.


On multipurpose integrated contact lenses:

The next challenge will be to integrate all the above functions and yield the first fully functional and stand-alone wireless contact lens. The day that such a device can be demonstrated may be much nearer than was imagined even a short while ago.


Several interesting articles on 3C-ICs from Semiconductor International:

Semiconductor Technologies

"Graphene May Have Advantages Over Copper For Future IC Interconnects":

Beyond resistivity improvement, graphene interconnects would offer higher electron mobility, better thermal conductivity, higher mechanical strength and reduced capacitance coupling between adjacent wires.


Because graphene can be patterned using conventional microelectronics processes, the transition from copper could be made without integrating a new manufacturing technique into circuit fabrication.


Scientists at the Forschungszentrum Dresden-Rossendorf (FZD) research center have been able to produce superconducting germanium for the first time.


At Semiconductor International: "IMEC Tips 10 nm Options at Tech Forum". One line that links nicely with the last paragraphs of the previous article:

Heyns said that recent studies at IMEC revealed that germanium oxide (GeO2), when grown under the right conditions on silicon, is actually a better insulator than the SiO2.

And the last paragraph, linking to the first article above:

Graphene, which is a zero-bandgap semiconductor with very high carrier mobility, is showing great promise, particularly for interconnects. While the current capacity for copper is ~106 A/cm2, it is ~109 A/cm2 for carbon nanotubes.

Thursday, June 11, 2009

Updates coming

Been on holiday the last weeks. Updates coming this weekend.

Saturday, May 16, 2009


Q&A with two signal integrity experts.

A Fourier transform is not the same as a Laplace transform.

A funny and informative video blog for lab rats (I like to think of myself as one).

A teardown of a "green phone":

[...] Above all, Motorola has shown that converting an existing design to a more ecologically friendly product does not require major innovation; it's something that can be done for just about any phone, and could've been done long ago.

The IEEE Spectrum slideshow on chip history.


An interesting technical note by NASA on a photodiode with low dark current and enhanced blue sensitivity.

An overview of MEMS development.

An article on capacitive sensors for patient monitoring.

And another one on an implantable sensor for cancer monitoring.

A technical article in two parts by an Intersil engineer :"Making Accurate Voltage-Noise and Current-Noise Measurements on Operational Amplifiers Down to 0.1 Hz". Again you need Explorer or this plugin for Firefox.


Nanoparticles to replace semiconductor LEDs.

More on graphene:

More on the PSP transistor model

An article in two parts on using the PSP model in RF. They can only be viewed with Internet Explorer unless you install this plugin for Firefox, but it somehow disbaled the clipboard functionality in my case. Or you can register in techonline and get it on pdf here.


On metal interconnects for next generation's 22nm technologies. And more on masks for 32 and 22 nm technologies.

An article on substrate integrated circuits (SiCs) for future Ghz and Thz electronic and photonic systems.

More buzz on 3D interconnects as the next singularity for the semiconductor industry. And a post which goes into some detail on the TSV technology which TSMC will offer soon.

A replacement for polyisilicon as gate material, by Freescale.

An interesting article on designing flexible printed circuit boards.


I don't know how widespread is the knowledge of this service, funded by the EU. IDESA offers very good seminars at no cost for european educational institutions.

I recently attended a very interesting seminar by Thomas Skotnicki on commercial 45 and 65 nm CMOS technologies. The talk was recorded for this series and it should be added to the website soon. There were two things that formed the backbone of his talk in my opinion. First, good understanding of the phyiscs behind the devices is of utmost importance to optimize the devices. And, second: going from one experimental device fabricated in the lab to reliable industrial fabrication of multimillion equal (or at least similar) devices is a very big leap.

As an analog designer, it was also good to hear yet another confirmation that feedback is probably the most important tool for smart analog circuit design.

He also mentioned (and showed examples of) the MASTAR software, which is available here.

Medical applications

A nice application note from Texas Instruments on medical applications of their chips.


Several links having to do with "power":

Sunday, May 3, 2009

Circuit theory

Two items of interest:

More on engineering history

Interesting article at EE Times by Rob Walker.

Semiconductor technology has enabled our computers, the Internet and 50-mpg cars. Your cell phone has more computational power than the computers did on the Apollo moon lander. Yet in spite of the semiconductor's seminal importance, semiconductor history is neglected by historians as "too new" and by the business media as "old news."

More on graphene

"Carbon nanodevices for sensors, actuators, and electronics" at SPIE.

[...]. Despite the promise of vastly superior performance of CNT and graphene-based devices, several fabrication issues need to be resolved to realize their full potential. [...]

Compare to the article which appeared recently in the spanish newspaper "El País" because the main researcher at M.I.T. working on graphene is spanish.

A more scientific explanation of the possible physics experiments done on graphene.

[...] Graphene has long been a theoretical model for 2D crystals. The unique properties of graphene excite theoretical physicists for another reason, too. It turns out that the quantum mechanics of electrons in graphene are identical to the quantum mechanics of massless relativistic particles, with the Fermi velocity (vF, about 10^6 m/sec) taking the place of the speed of light (c, about 3 × 10^8 m/sec). Graphene brings to benchtop equipment experiments that would otherwise require high energy particle accelerators.

New version of the GigE Vision standard

More info at Advanced Imaging magazine.

TSMC 40 nm technology

SemiSerious takes a look at the technology.

And TSMC admits that they still have yield issues.

Interesting application of stereo imaging

It's not that far fetched, but I must confess it hadn't crossed my mind: "The Secret Of Google's Book Scanning Machine Revealed".

Odd paper of the month

From the 2008 International SoC Design Conference: "Multiplier design based on ancient Indian Vedic Mathematics". The abstract:

Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). It mainly deals with Vedic mathematical formulae and their application to various branches of mathematics. The algorithms based on conventional mathematics can be simplified and even optimized by the use of Vedic Sutras. These methods and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, calculus (both differential and integral), and applied mathematics of various kinds. In this paper new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is based on generating all partial products and their sums in one step. The design implementation on ALTERA Cyclone -II FPGA shows that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier.

Sunday, April 19, 2009

Power and energy

It's a topic which pops up in this blog quite often. Here are a couple more interesting links:

Moving slightly aside from the topic, but putting it in a much wider focus, the subjects of power consumption, power management and the so-called "smart grid", should in my opinion be looked at from a global perspective. In that respect, this interesting article in the washington post looks into what I think is the most important problem in the new energy era: energy transport and its consequences.

Famous engineers

Via anablog, an amusing list of people I didn't know were engineers. I live on a street dedicated to one of them, which makes it the second place in a row where I live which is dedicated to an engineer, the previous one being Karl Ritter von Ghega.

One thing I will dispute with the writer is the ineptness of Edmund Blackadder.

Leakage power

A short overview on the problem of leakage in CMOS designs and what are people doing about it.

Interestingly, it is not only a problem for the obvious reasons, but for reasons which have much wider implications: "Leakage power analysis attack on cryptographic device realized in CMOS 90-nanometer technology". Which I guess links perfectly with this.

Plucked from the interweb

A list of miscellanous articles found in the last couple of weeks:

3-D packaging

Movements in this area:


One of the nice things of working in a research institute with a university nearby is that you can collaborate in very interesting projects.

Case in point. Some researchers from the Faculty of Medicine are working on brain interfaces. They use this chip, developed by colleagues in my group. They ask volunteers to participate in their experiments, and there I go:

Basically, they digitize EEG signal from 8 probes and correlate the waveforms with the stimuli. That way, I could type my name in the computer by "concentrating" on the letters I wanted to write. It still needs work, but the basic tools are there, and it's a matter of refining the algorithms.


While we are on the subject of brains, and if I may step aside from the main theme in this blog, allow me to recommend this recent article by Carl Zimmer, and this fantastic documentary.

Sunday, April 5, 2009


From the Electronics Letters issue of 24th March 2009: "Accuracy of PSP and BSIM4 models in determination of IP3 compression point" by A. Brambilla, G. Storti Gajani and C. Guardiani:

[...] Parameters of both the PSP and BSIM4 models adopted in the comparison have been fitted to a leading-edge 45 nm RF technology. The benchmarks show that the BSIM4 model is unable to capture the IP3 compression point whereas the PSP model yields the expected behaviour, thus enabling the determination of the correct value of IIP3.

Sunday, March 29, 2009

New materials and devices

Research on graphene devices continues at a nice rate:

[...] Palacios estimated that it will take as long as two years to demonstrate wafer-scale fabrication of the graphene circuitry.

Although with all these advances, there's a need to more skepticism.

Camera Interfaces

Two articles at the Advanced Imaging magazine sing the praises of different camera interfaces.

Meanwhile, some people take a more critical look at the new USB 3.0 standard.


It's becoming more and more clear that there is a push (at least in the U.S.) to make the power grid a driver for semiconductor business. These last couple of weeks have seen more coverage, research and industry efforts in the "smart grid" arena.

Meanwhile, the field of energy harvesting keeps on gaining momentum.

Tuesday, March 24, 2009

Patents, history and the origins of the CMOS image sensor

Techon reports about the patent fights of Caltech regarding fundamental technologies in the area of CMOS imagers. Without knowing the details, it's difficult to form an opinion on the rightness and/or rightneousness of the lawsuit. Nevertheless, the claim done in the article is that Hitachi invented the (passive) CMOS sensor. Without entering to discuss that claim, the first information on a silicon array image sensor I have comes from the thesis of a student of professor Theuwissen, which reports the first silicon sensor being published in 1966 in a paper by M.A. Schuster and G. Strull: "A monolithic mosaic of photon sensors for solid state imaging applications", IEEE Transactions on Electron Devices, vol. ED-13, pp. 907-912, 1966. The abstract reads:

Monolithic silicon mosaics of photosensor elements have been developed for solid-state imaging applications. The physical structure, design considerations, and performance characteristics of these electrooptical devices as applied to image converter applications are discussed.

The sensing monolith consists of a square 50 by 50 mosaic of phototransistor elements on 0.010 inch centers which are interconnected both by internally diffused strips and by vapor deposited surface bars. Fifty X and fifty Y external leads provide access to any individual element Xb Ya, of the mosaic. Fabrication of this 2500 element mosaic involves the techniques of planar passivation, epitaxial growth, solid-state diffusion, and thin-film vacuum evaporation.

A discussion of sensor operation includes mechanisms of phototransistor action, electrooptical conversion efficiency, and element-to-element crosstalk minimization.

An evaluation of the electrooptical transfer characteristics of the mosaic sensor elements are presented. Uniformity of element response
is typically better than 85% for response within a 3 : 1 range and 75% for response within a 2 : 1 range. Several shades of gray can be imaged simultaneously. The mosaic dynamic range extends over 3.5 orders of incident illumination energy or five orders of output photocurrent. The minimum and maximum detectable signals are approximately 10.0 nW and 1.0 mW, respectively. Sensitivity is of the order of 10^2 to 10^8 microA/mW in the linear portion of the transfer curve.

Incidentally, these two researchers worked at the time for NASA, at which JPL lab the active pixel sensor (APS) was invented about 24 years later. The patents that CalTech owns are from NASA's JPL.

It's a tricky thing to mix patent litigation with engineering history, and I find the Techon article referenced above very disappointing in this respect. I also sense a bit of nationalism in the thesis that Hitachi started it all, but that's just me.

Sunday, March 15, 2009

Miscellaneous articles

Focus on power

As an introduction to the ESC conference, this article introduces energy harvesting.

The main issue will not be as much how to generate energy, but how to deliver it without problems to the circuits that need it. In this direction, a colleague of mine presented her PhD work recently. You can get her thesis here: "Power Management Circuits for Power Generators".


Here is a nice intro to switching power supply design.

Here is another one on power supply cycling to reduce consumption in CPLD designs.

A good introductory tutorial to power MOSFETs.

And another one on Power-over-Ethernet designs.


This post does a good job of looking into the recent Lithium ion battery developments from MIT.

And to finish, a look at renewable energy production and storage at Scientific American.

More on black silicon

More figures and photos on this article at SPIE. Previously...

3D packaging special issue of the Proceedings of the IEEE

A good look at the many faces of 3D IC packaging in the January 2009 issue of the Proceedings of the IEEE.

Sunday, March 8, 2009

PCB design tips

Open source cameras

I posted recently about an open source camera. But there are more out there. The ones from Elphel look good.


Being in the lab testing a new system I designed or heped design, is one of the things I like more of this work. A few links to measurement topics:

Sunday, March 1, 2009

New materials and devices

A reversible diode.

A material which draws energy from any mechanical motion.


A very nice article by Paul Rako on oscillators.


Reverse-engineering the first GSM/GPRS CMOS power amplifier.

An article on direct conversion receiver designs.

A tutorial on sampling of band-pass signals.


Interesting article on EETimes on MEMS accelerometers.

A Tech Brief on a MEMS directional sound sensor based on the hearing organ of a fly.

A brief on a "High-throughput, on-chip, whole-animal screening at subcellular resolution".

And another brief on "Noninvasive mail inspection using terahertz radiation".


Different posts appeared during this week with a theme in common. Guess which.

Sensor conditioning circuits

A couple of articles from Planet Analog:

Sunday, February 22, 2009

Black Silicon

I really was expecting more from this interview with the founder of SiOnyx on the technology behind "black silicon".

For technical details, skip to the original press releases or the university research pages.

Or even better, check the papers or a couple of their patents describing the fabrication methods:

"The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns".

If they can use normal foundries as the interview suggests, this is really something.


I didn't expect back-side illumination to go mainstream this fast.

How Canon builds their camera prototypes.

And I just found this blog covering the world of image sensors (and thanks for adding my blog to the links)


This week brought the news of the confirmation of graphene semiconductor theory. If you want more technical, last year's DAC carried an interesting paper on the topic of graphene FETs. Yes, you can check the DAC proceedings online for free, with the papers, the slides and in some cases youtube links of the talk. Sweeeeet.


Two posts from on the effects on layout of the fabrication steps for nanoscale CMOS: "Lithography for dummies" and "Gridded design rules with lines and cuts".

3-D integration

Or putting chips on top of each other. There will be more detailed posts here, but business is starting to grow in this area. Faster than I thought:


EDA is always on the receiving end (find me an analog designer who is happy with Cadence DF...), so it's refreshing to find a blog such as EDA Graffiti (although too "digito-centric"). From this blog, two nice posts from last week: "EDA: not boring enough" and "The book that changed everything".

In the analog end of EDA, yet another company promising to solve the DfM conundrum via statistical simulations.

Energy harvesting

Managing it in an efficient way is as important (or even more) as harvesting the energy. Nevertheless, it's this last topic which attracts more headlines, and articles such as this (two months old) overview at Electronic Design.

MSc thesis at IMEC

Interested in doing your MSc thesis at IMEC? You can get the whole list here. Why a MSoft Word document? Good question...

The first six in the section on "heterogeneous integrated microsystems" fall under my supervision:

  • Study and realization of a hardware and software platform for imaging systems.
  • Software platform for emulation of image sensor systems.
  • Design of an analog-to-digital converter (ADC) for use in an image sensor readout-circuit.
  • Design of an array of ADCs (analog-to-digital converter) for image sensors.
  • Design of a general purpose digital circuit for the control of an imaging array.
  • Continuous-time/asynchronous signal processing for bio-medical sensor systems.

If interested, follow the procedure described in the document.

Sunday, February 15, 2009

Miscellaneous ISSCC posts

From the ISSCC coverage last week:


Reducing the size of cameras is a strong driving force nowadays. Two approaches:

Meanwhile, CCDs are still very much in the picture (pun intended), as this analysis done by ChipWorks of a sensor used by Canon shows.

More on high speed signaling

Plenty of stuff on this area last week:

ADCs and windowing

Related to the piece of software I mentioned earlier, a two part article on Planet Analog: "Windowing high-resolution analog/digital converter data" (Part 1, part 2)

Tuesday, February 10, 2009


In the latest edition of EETimes (pdf available, but individual article not yet): "Cell phones warm up to magnetic coupling" by Rick Merritt. It's about charging a battery wirelessly.
Somehow, it manages to mention environmental concerns as a driver for this technology, and yet no mention in the whole article of the power efficiency of these systems. Will you waste more power with this charger than with a conventional one? Most likely.

Saturday, February 7, 2009

High speed signaling

A very interesting area to work on, if you can. A combination of analog and digital IC design, PCB design, system design... And with a lot of coverage lately. A sample from the last week:

  • "Maximize high-speed signal integrity with the right choice of cables, layout, and equalizer ICs" parts one and two at Planet Analog. Although I do not like the random approach to decoupling capacitors. I'm trying to prepare a longer post on that issue, which does not attract as much attention as it deserves.
  • "Panel eyes road to 25 Gb/s backplanes", the new frontier for good ole Ethernet.
  • "High speed systems defy test, tools", or just a few of the hurdles ahead.

More on FPGA

And still another nice technical article on FPGAs.

What's coming on FPGA world

A nice analysis of the new stuff coming from Xilinx, which goes beyond copypasting the press release.

ADC data analysis software

I just discovered this nice new tool for analyzing ADC output data: Wavevision5 from National Semiconductor.


Layoffs are falling hard these days in this industry. Although my employer is relatively safe in this area, they announced a freeze in new hirings.

Anyway, EDN has two interesting articles on the topic: Why the layoffs if we're still profitable? and Life after layoffs: How to move forward after a job loss.

EE Time's 60 startups list

EE Times has updated its 60 startups list.

A quick scan reveals that almost half of them are in California, and the second country with more is the UK, with eight. About one quarter are active in mixed signal/RF design.

Some links are not right, or at least the one for Gigle, the only company from my country in the list (oddly, their website is copyrighted only until 2007...).

Monday, February 2, 2009

Weekly roundup at Planet Analog

For those of you who do not know about it, you should check every week the "Also of Interest and Elementals" collection of links by Bill Schweber over at Planet Analog.

Here's this week's collection. I found particulary interesting the one on Defected Ground Structures.

Sunday, February 1, 2009

BioEngineering: ViroChip

Joe DeRisi, in a 2006 talk from TED, on the ViroChip:

Science and Engineering

Over at Test & Measurement World, an editorial on which are the differences between science and engineering.

Engineering history

Paul Rako gives a lesson on design history (or at least a hint on what that lesson should be).

Engineering history is a neglected field, and the effort of the IEEE history center is to be commended.

Thursday, January 29, 2009


If you are an IEEE member and have access to Xplore on your company/university, a non-scientific but still interesting survey on sensors at the IEEE Instrumentation and Measurement Magazine.

Else, what are you waiting for!

Cheap cameras

And I'll start with some stuff about cameras.

First, a teardown of a $9.99 tiny camera, and the simplicity of its insides.

And related, although way more interesting (for me at least) is this "open source" camera system: the leanxcam from Supercomputing Systems. Schematics and sofware free to use.

Initial condition

So when I find an interesting link/article/tool relevant to our job I send an email to my colleagues, which has ended up with me lovingly referred to as "the spammer". I've then decided to just post them somewhere and whoever wants to check what I find is free to do so.

What to expect? Well, I'm an IC analog designer working mostly on image sensors. But devices, applications, other areas (RF, digital) also interest me. So anything remotely "electronic" is bound to pass by here. Possibly including also other engineering areas.

Let's see how this goes...